0.35µm CMOS Application Notes

Applications

Digital, Analog and Mixed Signal Systems

Key Features

  • 0.35µm CMOS polycide-gate process
  • Four unrestricted layers of metal
  • Second layer of poly for linear capacitors and linear resistors
  • Peripheral cells with high driving capability
  • High performance digital and mixed signal capabilities

Key Specifications

  • C35B3C0 2P/3M 3.3V CMOS Mixed Signal, PIP
  • C35B3C1 2P/3M 3.3V CMOS Mixed Signal, PIP, 5V periphery
  • C35B4C3 2P/4M 3.3V CMOS Mixed Signal, PIP, high-res poly, 5V periphery
    • Minimum Feature Size: 0.35µm gates
    • Supply Voltage: CMOS 3.3V; periphery up to 5.5V
    • Gate Delay: 0.10ns (NAND2 typical)

Description

austriamicrosystems' 0.35µm CMOS process family is fully compatible to the 0.35µm mixed signal base process licensed from TSMC. The high density CMOS standard cell library optimized for synthesis and 3- and 4-layer routing guarantees highest gate densities. Peripheral cell libraries are available for 3.3V and 5V with high driving capabilities and excellent ESD performance. Qualified digital macro blocks (RAM, diffusion programmable ROM and DPRAM) are available on request. A variety of high performance analog-to-digital and digital-to-analog converters can be provided for integration on the same ASIC.

Design Kits

SYNOPSYS:

  • Digital standard cell libraries

CADENCE:

  • Digital and mixed-signal HIT-Kit for Analog Artist
  • Build Gates synthesis libraries
  • VERILOG Simulation Models
  • Digital standard cell libraries for Silicon Ensemble
  • Spectre simulation parameters
  • Device layout generators (pcells)
  • RAM, ROM, DPRAM compilers in qualification
  • Analog macros

Simulation Parameters for: ELDO, HSPICE, PSPICE, SABER, SMASH, SPECTRE, ADS

Documentation & Support

Design Rules & Process Parameters documents and simulation parameters are available at austriamicrosystems' technical web server http://asic.austriamicrosystems.com

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