High Voltage Technology Selection Guide

Selection Guide:

Process Name

H35B3KC

H35B3LC
***

H35B4KD
***

H35B4LD
***

H35B4D3

CXT

CXY

CXZ

Process features

2P, 3M, HRP, 20V

2P, 3M, HRP, 5V, 20V

2P, 4M, HRP, TM, 20V

2P, 4M, HRP, TM, 5V, 20V

2P, 4M, HRP, TM, S, 5V, 20V

2M, 1P, S

2M, 2P, S

2M, 2P,
HRP, S

Number of masks

18

21

21

24

27

15

16

17

Max. operating
voltage
HV-NMOS [V]

50

50

Max. operating
voltage
HV-PMOS [V]

50

50

specific R_on*
HV-NMOS
[Ohm mm^2]

0,11

0,34

specific R_on*
HV-PMOS
[Ohm mm^2]

0,29

0,8

Drawn LVMOS
Channel Length
[µm]

0.35

0.8

Operating voltage
LV-MOS [V] **

3,3V, 5 V

5V

Max. gate
voltage [V]

3,3V, 5 V, 20V

5V, 20V

2M

 

2 metal layers

3M

 

3 metal layers

4M

 

4 metal layers

1P

 

1 poly layer

2P

 

2 poly layers

HRP

 

high resistive poly

S

 

substrate related LV devices

TM

 

thick metal layer

5V

 

5V gate oxide

20V

 

20V gate oxide

     

*

 

the specific Ron is calculated from the minimum transistor source drain pitch. The value does not include design related substrate contacts or guard rings.

**

 

Isolated LVMOS logic can be raised up to 50V Design blocking voltage

***

 

Process option available on request

Back to Top
Print Content Bookmark Page E-Mail Page