0.8µm Process Technology
Applications
- fast mixed signal circuits
- ATM up to 1.24 GBit/s, wireless communication up to 2.4 GHz
- high speed AD/DA converters up to 200 MHz
Description
The austriamicrosystems BiCMOS process is based on the proven 0.8µm analog CMOS process and includes an additional high performance analog oriented bipolar module providing mixed signal ECL, BiCMOS, and CMOS design capabilities.
Key Features
- 0.8µm CMOS Si-Gate process technology with poly emitter 12 GHz bipolar module
- Two unrestricted layers of metal and two layers of poly for linear capacitors
- Poly-to-poly capacitors (BYE, BYQ), High resistive poly options (BYQ)
- Optimized for RF applications
- ECL, CML, BiCMOS and CMOS cell library
- Full swing BiCMOS outputs allow unrestricted mix of CMOS and BiCMOS core cells
- ECL, TTL and CMOS interfacing capability
- Peripheral cells with high driving capability
- Fully differential ECL/CML cell variants for noise immunity
- High performance mixed signal capabilities
- IEEE 1149.1 boundary scan macros/cells
Key Specification
- BYE 2.5-5.5V p-sub, 2-metal, 2-poly, poly-poly capacitors
- BYQ 2.5-5.5V p-sub, 2-metal, 2-poly, poly-poly capacitors, hr-poly
Documentation & Support
Design Rules & Process Parameters documents and simulation parameters are available at austriamicrosystems' technical web server http://asic.austriamicrosystems.com