Engineering Service
Customers developing and designing their own ASIC usually provide a verified design database to austriamicrosystems.
The design interface for foundry projects can be provided in the following formats:
- Verified design netlist with austriamicrosystems standard cells, referred to as semivalidated netlist (SVNL) interface in Cadence, Mentor, Synopsys, Verilog or EDIF format
- Verified layout database. Format is GDSII. The foundry input document specifies the interface requirements
Today more than 90% of the foundry projects entrusted to the company include a verified layout database interface.
An experienced team of engineers and project managers is responsible for the handling of all silicon foundry projects during the development phase. The same team is also responsible for the organization and execution of the austriamicrosystems´ multiproject wafer train service. Sales offices are updated daily on the foundry project development status.
A project engineer is assigned to each new foundry project and is in charge of the execution of the technical and administrative tasks from database input through to the manufacture of samples and or volume production. austriamicrosystems provides a variety of proven foundry services and a wide range of special services such as: