Design Verification
For GDSII database input, austriamicrosystems offers a layout verification service based on our sign-off check tools from several EDA tool providers.
The following checks can be performed upon request:
- DRC, ERC, LVS and ESD Rule Check
- Electrostatic Antenna Check
- GDSII Stream Data Check
DRC/ERC/LVS are the design verification routines before mask making. If a customer design input is an unverified GDSII layout austriamicrosystems will run DRC/ERC/LVS, provide report files and assist in interpreting these. For the LVS a Verilog or SPICE netlist or schematic files (Mentor, Cadence) are required.