Special Engineering Services
Design Review
If the circuit is anticipated to go into high volume production at austriamicrosystems, a design review at austriamicrosystems is recommended.
Should problems or inconsistencies are found which might result in a high development risk or low production yield, the customer will be responsible for the corrections.
Design Verification
DRC/ERC/LVS are the design verification routines before mask making. If a customer design input is an unverified GDSII layout, austriamicrosystems will run DRC/ERC/LVS, provide report files, and assist in their interpretation. For the LVS, a Verilog / SPICE netlist, or schematic files (Mentor, Cadence) is required.
Test Vector Generation
Verification of the test vector database with customer specified input and expected output stimuli can be offered. A test pattern conversion and verification tool is delivered with the austriamicrosystems Design Kits.
Matrix Runs
Some critical products, particularly when designed on another foundry's design rules, may require an experimental wafer run, combining different process parameter sets in order to define the optimum for regular production.
Hot Lot Service
Customers request may pend available capacities, hot lot services for wafer fabrication can be provided on best effort basis. On special request shorter production times than indicated may be accommodated. Please contact your local sales office for further information.
Process Stop
A process stop occurs when a wafer lot or part of it, by request of the customer is not completely processed. The wafers will be kept on hold for a maximum period of 12 weeks from the date of the stop. This allows corrections of mask levels past the stop position and may save considerable time during redesign cycles.
Span Times from Engineering Samples Approval to Prototypes
As soon as the company receives a written approval of the engineering samples the development of the test program will start. While this will typically take 4 weeks for digital circuits, it may require considerably more time for analog circuits. This can be partly compensated if the customer provides the inputs for test program development in advance and an understanding can be established with the customer on how to proceed.
Lead Times
Below, the lead times refer to the simplest case, i.e. no extra services are required. Consequently, whenever special services are required, span times may increase:
| Clustering of multi-product wafer database for dedicated runs | 3 days |
| Design rule check | 5 days |
| Layout versus schematic check | 5 days |
| Verified layout database to engineering samples | typically 6 - 12 weeks, depending on process |
Products for Engineering Evaluation
Products will normally be untested ceramic packages. Alternative samples may be provided. While the company will make reasonable efforts to provide the desired quantity of deliverables, only the following minimum numbers will be guaranteed:
| Packaged engineering samples or prototypes | 10 |
| Dice in waffle pack | 15 |
| 8 inch Wafers | 2 |
In exceptional cases higher numbers of engineering samples may be provided according to prior arrangements. However, the company discourages the use of engineering samples for commercial sale to the end customer for reasons of product liability. If a customer requests a higher number of engineering samples, austriamicrosystems will require formal evidence that such samples are needed for internal laboratory use.