AS1153 LVDS Receiver IC
Dual 260Mbps LVDS Receiver, SOIC 8-pin
Description
The AS1153/57 are Dual flow-through LVDS (low-voltage differential signaling) receivers which accept LVDS differential inputs and convert them to LVCMOS outputs. The receivers are perfect for low power low-noise applications requiring high signaling rates and reduced EMI emissions.
The devices are guaranteed to receive data at speeds up to 260Mbps (130MHz) over controlled impedance media of approximately 100Ω. Supported transmission media are PCB traces, backplanes, and cables.
The AS1153 uses high impedance inputs and requires an external termination resistor when used in a point-to-point connection.The AS1157 features integrated parallel termination resistors (nominally 107Ω), which eliminate the requirement for discrete termination resistors, and reduce stub lengths.
The integrated Failsafe feature sets the output high if the inputs are open, undriven and terminated, or undriven and shorted.
All inputs conform to the ANSI TIA/EIA- 644 LVDS standards. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS outputs.
The devices are available in an 8-pin SOIC package.
Key Features
- Guaranteed 260Mbps Data Rate
- Flow-Through Pinout
- Failsafe Circuit
- 300ps Pulse Skew (Max)
- Single +3.3V Supply
- Integrated Termination (AS1157/58)
- Conform to ANSI TIA/EIA-644 LVDS Standards
- Operating Temperature Range: -40ºC to +85ºC
- 8-pin SOIC Package
Applications
The devices are ideal for digital Copiers, Laser Printers, Cellular Phone Base Stations, Add/Drop Muxes, Digital Cross-Connects, DSLAMs, Network Switches/Routers, Backplane Interconnect, Clock Distribution Computers, Intelligent Instruments, Controllers, Critical Microprocessors and Microcontrollers, Power Monitoring, and Portable/Battery-Powered Equipment.
Block diagram for AS1153 LVDS Receiver IC
AS1153 Dual 260Mbps LVDS Receiver Block Diagram