AS3530 Mobile Entertainment IC

Description

The AS3530 is austriamicrosystems' digital system for its new generation mobile entertainment platform. It's flexible architecture allows single chip solutions for high performance power optimized audio and video products with minimum count of external components.

The device can be configured in two ways: for pure audio products the video decoder and parts of the main memory can be configured into power down. For video applications the video decoder hardware will be enabled and the speed of the system will be scaled to the actual demanded video decoder complexity and resolution. All video decoder features for H.263/MPEG-4/H.264 and VC-1 are implemented in a dedicated video hardware accelerator for minimal power consumption and also ultra low main processor load.

Using low power deep submicron technology gives outstanding performance in terms of power consumption and utmost integration densities for embedded on-chip RAM and ROM areas.

The AS3530 is intended as microcontroller chip including all digital function blocks necessary for a portable audio or video player. These function blocks include onchip RAM and ROM memories, interface blocks for data transfer and storage like USB, IDE, NandFlash, MMC, SD, SDIO, CE-ATA, hardware acceleration for video decoding, clock generation and digital power optimisation functions.

Based on the ARM926-EJ with large on-chip instruction and data caches and integrated MMU, the system gives full support for all kinds of operating systems from simple RTOS implementations up to Symbian OS, micro Linux and Windows CE. For all audio input/output and power management it is intended that the chip is used in combination with austriamicrosystems audio AFE products (e.g. AS3514/ AS3515/AS3517/AS3518/AS3519). For the chip family MCM derivatives with integrated AFE and integrated mobile SDRAM are planned as future products. austriamicrosystems provides a total system solution reference design including all necessary software blocks for low level HW drivers, device IO functions and a dedicated reference application with common audio and video features. austriamicrosystems runs a comprehensive software partnership program which allows authorised software partners to provide variety of audio or video extensions, applications or total solutions based on austriamicrosystems powerful portable multimedia platform.

Key Features

1. Basic System

• ARM926-EJ RISC Controller
  • 32/16 bit RISC architecture
  • 16-bit Thumb instruction set
  • ARMv5TEJ extended DSP instruction set and single cycle MAC
  • Memory Management Unit
  • Embedded ICE JTAG debug interface
  • 16KB Instruction + 16KB Data Cache
  • Up to 400 MHz clock speed
  • Power consumption: 0.265 mW/MHz including caches at typical conditions
  • 32/16 bit RISC architecture
• Memory
  • 512 KByte embedded SRAM connected to AHB1
  • 128 KByte ROM (128KB bootrom + 32KB GF-table)
  • 32 KByte embedded SRAM connected to AHB2 as buffer memory within AHB2 bus domain
  • External memory controller supporting
    • Support for 16/32 bit data width
    • Synchronous/asynchronous SRAM/Flash interface
    • SDR DRAM (single data rate DRAM)
    • Supports 2 static and 2 dynamic external memory devices
    • Support three IO voltage levels: 1.8/2.5/3.3 V
    • Pads with programmable drive strength
    • 133 MHz max external memory clock frequency
• AMBA Bus
  • Two AHB bus segments
    • AHB1 with all Core/Memory high performance elements running up to 150 MHz
    • AHB2 with all peripheral interface blocks running at max 100 MHz bus speed
  • AHB bus bridge between AHB1 and AHB2
    • Synchronous 1:1 mode
    • Asynchronous mode
  • AHB interconnect matrix for high throughput
    • AHB to APB bridge
    • Connected to AHB2
• DMA controller
  One DMA controller located in each of AHB1 and AHB2 bus domain
  • DMA1 in AHB1 bus domain
    • 8 simultaneously opened DMA channels
    • 16 DMA request
  • DMA2 in AHB2 bus domain
    • 8 simultaneously opened DMA channels
    • 32 DMA requests
• Interrupt Controller (VIC)
  • Support for 32 non-vectored interrupts
  • Support for 32 vectored interrupts
• PWM outputs
  • Four PWM output channels each channel can run independently or synchronized
  • Period, pulse width and phase defined by 8-bit registers (phase only in synchronized mode)
  • Two independent rotary decoders with programmable glitch filter
  • Programmable count direction
  • Programmable interrupt on zero count
  • Zero count can stop PWM modulators
• Timer and Watchdog
  • Two independent timer blocks (A+B) with two 32-bit counters each
  • Two timer trigger event inputs
  • watchdog
• Chip Control Unit
  • Two independent 1 GHz PLL generators (PLLA, PLLB)
  • Internal 24 MHz oscillator
  • Optional usage of external oscillator
  • Four programmable clock outputs
  • Chip version number
  • Control of IO multiplexing
  • Universal spare registers
  • Clock gating / block enables
  • JTAG disable bit
• Keyscan Controller
  • Configurable 1x4 to 4x4 or 1x8 to 8x8 matrix
  • Low power mode
  • Interrupt generation
• RTC
  • Integrated ultra low power 32 KHz oscillator
  • Separated power supply
  • Wakeup can be triggered by RTC
  • Suspend mode with all clocks stopped, resume by RTC timer
• IMON
  • Intelligent hardware monitor for bus and system profiling for continuous system monitoring and power optimisation.
  • Very flexible selection of input events
  • Monitoring averaging or peak conditions
  • Scalable counters
  • Programmable interrupt generation
• OTP
  • 256 Bit one-time-programmable memory
  • Contains unique ID

2. Interfaces

• Audio Interface
  • Two I²S input interfaces
    • FiFo (32x48) buffered
    • DMA support
    • 14/24 bit modes
    • SPDIF input bridge
  • Two I²S output interfaces
    • FiFo (128x48) buffered
    • DMA support
    • 16/18/24 bit modes
    • SPDIF output bridge
  • Synchronous I²SIN to I²SOUT streaming mode
• USB 2.0 HS & OTG Interface
  • Up to 480Mbit/s transfer speed
  • USB 2.0 HS/FS physical including OTG support
  • USB 2.0 HS/FS digital core including OTG host
  • Dedicated dual port buffer RAM
  • DMA bus master functionality
  • Total of seven endpoints (1xCONTROL, 3xIN, 3xOUT)
• IDE Host Controller
  • Supporting Ultra ATA 33/66/100 modes
  • Programmable IO and Multi-word DMA capability
  • Dedicated dual port buffer RAM
  • DMA bus master functionality
• NandFlash Interface
  • 8 and 16 bit flash support
  • 3, 4 & 5 byte address support
  • DMA support
  • Basic hardware ECC for SLC
  • Extended BCH error correction for MLC (correction of up to 8 errors within 512 byte)
  • Caching of ECC data for 2K/4K/8K page sizes to write ECC data to spare region
• MMC/SD Interface
  • Mobile Storage controller supporting various standards
    • SD card according to SD Phys. Layer Spec V2.0
    • SDHC card according to SD Phys. Layer Spec V2.0
    • SDIO interface according to SD spec part E1,SDIO Spec V2.0
    • Multimedia Card according to MMC Spec V4.2 including MMCplus and MMC Mobile
    • Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.2)
  • Other Features
    • Integrated 2048 byte FiFo
    • Separate clock for bus interface and card interface
    • 1, 4 or 8 bit data width for MMC card IF
    • 1, 4 bit data width for SD card IF
    • AMBA AHB bus interface
• Memory Stick Interface
  • Memory Stick and Memory Stick Pro support
  • 20 MHz serial, 40 MHz parallel clock
• Synchronous Serial Interface
  • Three independent SSI interfaces
  • Master/slave
  • TX/RX FiFo buffering (16 byte)
  • DMA support
  • 8/16 bit support
• 2-wire Control Interfaces
  • Three independent I²C interfaces
  • Master/slave function
  • FiFo buffering (16 byte)
  • DMA support
  • Max 400 KHz speed
• UART
  • Three independent UART interfaces
  • Baud rates up to 2 Mbit/s
  • Internal RX/TX FiFo buffering (64 byte)
  • DMA support
  • Irda SIR Encoder/Decoder
• General Purpose IO
  • Most of the PINs configurable as GPIO
  • Configurable drive strength
  • Configurable pull-down function
  • Each GPIO PIN can be used as programmable interrupt source
• Generic Infrared Interface
  
  • Modulated or digital transmit and receive
  • Independent transmit and receive FiFo buffers (16 entries each)
  • Direct interrupts for transmit and receive FiFo level monitoring
• CAN Bus
  • ISO011898 CAN specification V2.0B compatible
  • 11-bit and 29-bit identifiers
  • Bit rates from 125 Kbit/s to 1 Mbit/s
  • Total of 8 transmit and receive buffers
  • 3 identifier filters
• XM Satellite ready
  • Integrated XM DT interface
  • LVDS interface
  • Uses internal PLLB for generation of 45.1584 MHz clock
• Display Interface
  Two display output interfaces are available: either DBOP for simple small resolution displays or full RGB/LCD controller IF for high resolution displays
• DBOP
  • Configurable interface for different types of uController
  • System interfaces (Intel 80xx or Motorola 68xx style)
  • FiFo buffer (128x32) and DMA support
  • 8 or 16 bit modes
• LCD Controller
  • FiFo input data buffer (dual 16x64)
  • Supports single and dual panel mono STN
  • Supports single and dual panel color STN
  • Supports TFT color displays
  • Wide range of programmable resolutions: 320x200, 320x240, 640x200, 640x240, 640x480, 800x600,1024x768
  • 1/2/4/8 bpp palettized color for STN or TFT
  • 16 bpp true color STN or TFT mode
  • 24 bpp true color TFT
  • TFT modes with 12 bpp direct 4:4:4 RGB, 16 bpp direct 5:5:5, 16bpp direct 6:6:6 and 16bpp direct 5:6:5 both with common intensity bit), 24 bpp direct 8:8:8
  • Hardware cursor support for single panel displays
  • Programmable parameters for all key parameters (frequency, timings, resolution, bpp, color modes,.)
• Video Output
  CCIR-656 compatible pixel output port to support an external PAL/NTSC video encoder
  • 27 MHz data rate
  • 8-bit parallel data IF with YCrCb 4:2:2 encoding

3. Audio Engine

• Audio Accelerator
  • Ultra low power accelerator for decoding of MP3, WMA and AAC
  • Includes ten-band equalizer with 64 steps (-20 ÷ 20 db gain) and 32-step volume control
• MP3 features
  • 9 MHz clock frequency for MP3 decoding with 320 kbit/s input bit rate / 48 KHz audio sampling rate
  • Support MPEG-1 layer III and MPEG-2 layer III (ISO11172-3 and ISO13818-3) formats
  • Support for constant and variable bit rate from 8 to 320 kbps
• WMA features
  • WMA V8 and V9 compatible WMA decoder
  • Support of bit rates from 5kbps up to 382 kbps
• AAC features
  • AAC with support of CBR and VBR
• Audio Post-Processor
  For flexible audio signal processing an internal audio matrix is available together with a audio mixer, equalizer and sample rate converter.
  • 5 band graphic equalizer
  • I²SIN input sample rate conversion for audio mixing with signals running on other sampling rate
  • Audio mute
  • L/R channel swap
  • Gain attenuation
  • Limiter modes
• Security Engine
  • AES ciphering supporting 128 bit keys with ECB, CBC and CTR block cipher modes
  • DES and 3-DES ciphering supporting ECB and CBC block cipher modes
  • RC-4 ciphering supporting 40-bit and 128-bit key expansion modes
  • All cipher modes support both encrypt and decrypt operations
  • SHA-1 and MD-5 hashing algorithm with support for HMAC mode (key sizes of 1 to 64 byte)
  • Power optimized True Random Number Generator (TRNG) supporting initial seeding and 32-bit random word every 128 clock cycles

4. Video Engine

The video engine consists of a video accelerator and of an independent video postprocessor. Features of the video postprocessor can be used independently of the chosen video decoding algorithm (running either in the video accelerator or in software).

• Minimum power consumption of HW video engine
• < 18mW for H.264 PAL/NTSC resolution
• Video Accelerator
  • MPEG 4 simple profile, Levels 0 - 5
  • H.263 profile 0, Levels 10 - 70
  • H.264 / AVC Baseline, Levels 1 - 3.1
  • VC-1 (Windows Media Video 9) main profile, levels Low, Mid and High
  • JPEG Baseline DCT, sequential
  • Video resolutions (for MPEG-4/H.263/H.264/VC-1)
    • Up to 720x576 at 25 fps (PAL/DVD) or
    • Up to 720x480 at 30fps (NTSC)
  • Ultra low CPU load < 3MHz
• Video Post-Processor
  • Integrated colour space conversion YCbCr to RGB
  • Proprietary scaling algorithms for better quality on handset resolutions
  • Image rotation
  • Cropping function for viewing large images on small displays in original size
  • Masking feature for easy user interface implementation
  • Alpha blending support for two variable sized regions
  • Picture-in-picture support

5. Extended System Features

• Boot Options
  The chip contains an on-chip ROM Bootloader that supports booting from various kinds of external flashdevices. During boot, the application firmware is loaded from the external flash device into the RAM. In addition to this boot functionality, also the firmware programming and firmware update is supported.

• NandFlash
• External static Flash (MPMC)
• Serial NOR Flash
• IDE
• SD/MMC/SDIO/CE-ATA
• Bootloader concept with 1st/2nd level loader for initial firmware programming and firmware update
• Secured firmware update mechanism Modes of operation
• Normal operation
• Hibernation mode (clock stopped)

6. Power Consumption

• Playback use case: MP3 / AAC / WMA playback 128kbit/s, 44.1 KHz, output level 150 mVrms, no external memory. Depending on output quality, following power consumption values are achieved. Standby use case: clock stopped, only voltage generation for keeping memory content is on, system willwakeup by timer interrupt.

7. Packaging

• Single chip CTBGA 10x10 mm with 0.5 mm ball pitch, 280 Balls

Applications

Portable Digital Multimedia Players with ultra low power consumption

Block diagram for AS3530 Mobile Entertainment IC